1. Field of the Invention
The field of the invention relates generally to buffers and more particularly to a power saving buffer circuit that may be used to interface a TTL logic circuit to a CMOS logic circuit, for example.
2. Background
Conventional circuits often involve interfaces between different logic families, such as TTL and CMOS. Often the different logic families represent high and low logic levels using different voltage levels. For example, a TTL circuit may represent a high logic level with a voltage in the range of about 2.4 to 5 volts, and it may represent a low logic level with a voltage in the range of about 0 to 0.8 volts. A CMOS circuit, on the other hand, may represent a high logic level with a voltage in the range of about 4.7 to 5 volts and a low logic level with a voltage in the range of about 0 to 0.3 volts. Accordingly, a buffer that interfaces a TTL circuit to a CMOS circuit, for example, typically must convert TTL high logic voltages to CMOS high logic voltages and TTL low logic voltages to CMOS low logic voltages.
FIG. 1 illustrates a conventional TTL to CMOS buffer 100 that accomplishes such a conversion. Buffer 100 includes two invertors 106 and 108. In operation, when input 102 is at a TTL low level, output 104 is at a CMOS low level. In this state, transistor 112 is on while transistor 1 14 is off, pulling node 110 to a high logic level (e.g. V.sub.DD). Inverter 108 inverts the high level at node 110 to provide a CMOS low logic level at output 104. When input 102 is at a TTL high level, on the other hand, output 104 is at a CMOS high level. In this state, transistor 112 is off while transistor 114 is on, pulling node 110 to low logic level (e.g. ground). Inverter 108 inverts the low level at node 110 to a CMOS high logic level at output 104. Inverter 108 can be constructed in the same manner as inverter 106. If so, it will provide a CMOS high level that corresponds to reference voltage 120 (e.g. V.sub.DD) and a CMOS low level output that corresponds to reference 122 (e.g. ground).
Under ideal conditions, buffer 100 typically consumes little power when a TTL high (e.g. about 4.7 volts) or a TTL low (e.g. about 0.4 volts) logic level is applied to input 102. As described, either transistor 112 or transistor 114 typically will be off, and no current path will exist from V.sub.DD to ground. As is known in the art, however, this buffer typically consumes power when switching between high and low logic levels. In particular, during switching, both transistors 112 and 114 may be on simultaneously, enabling a switching current to flow from V.sub.DD to ground. Please see N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A System Perspective, Addison-Wesley Publ. Co. 1988, pp. 43-49 for a discussion of the operation of inverter 106 and this switching current.
In addition, some modern systems have been using lower TTL high logic voltages for speed, power savings or other reasons. A system might use an "intermediate" TTL high voltage of about 2 volts, for example, which is below the 2.4 to 5 volts high logic voltages used in other applications. Where such an intermediate voltage is used, buffer 100 undesirably may consume power even under static conditions. Such an "intermediate" high logic level, for example, may not provide a high enough voltage to turn off transistor 112 when input 102 is high. Accordingly, both transistors 112 and 114 may be on simultaneously and a current may flow from V.sub.DD to ground even after input 102 has fully completed the transition from a low logic level to a high logic level, for example. Such a "static" current may prevent a system designer from meeting the desired power constraints of a particular system. This static power consumption can be even more important if it occurs in a modern low power system, such as some type of portable electronic equipment. If the lower voltage was originally used to reduce power consumption, for example, this static current can reduce the benefits obtained from the lower voltage.
Efforts have been made to address this issue in TTL to CMOS buffers. Please see, for example, U.S. Pat. No. 5,304,867 to Morris entitled CMOS Input Buffer With High Speed and Low Power, U.S. Pat. No. 4,471,242 to Noufer et al entitled TTL to CMOS Input Buffer and U.S. Pat. No. 5,151,620 to Lin entitled CMOS Input Buffer With Low Power Consumption. Unfortunately, a technique used to reduce a buffer's power consumption may itself consume undesirable amounts of power. Alternatively, the power savings obtained may be limited by concerns related to buffer speed or, for other reasons, may simply fail to achieve the desired level of savings. Power saving techniques may also require undesired amounts of additional circuitry.
The Morris patent, for example, biases a transistor 27 to provide a resistance means for reducing the power consumed by a buffer. This patent states, however, that a lower limit is placed on the power savings of this design because there is an upper limit on the resistance that this transistor can provide. In particular, it states that this transistor must have a resistance low enough to maintain node 29 at a high level. Please see Morris, Col. 2, line 45-Col. 3, line 7.
In addition to power consumption, conventional logic buffers may not provide the desired immunity to noise. FIG. 2 illustrates a hysteresis characteristic that may be desired in a logic buffer that converts between logic levels of two different logic families. Such a hysteresis characteristic may enable a logic buffer to achieve a desired level of noise immunity. As illustrated in FIG. 2, the input voltages represent logic levels according to a first logic family. V.sub.TL is the input voltage at which a high to low input transition causes the output voltage to transition from a high logic level V.sub.OH to a low logic level V.sub.OL. V.sub.TH is the input voltage at which a low to high input transition causes the output voltage to transition from a low logic level V.sub.OL to a high logic level V.sub.OH V.sub.OL and V.sub.OH are the low and high logic output voltages, respectively, of a second logic family to which the input low and high voltage levels are converted. V.sub.IL is an expected input low logic level and V.sub.IH is an expected input high logic level of a particular system or circuit design. This hysteresis characteristic can operate to reduce sensitivity to noise. Unfortunately, conventional buffers may not achieve the desired hysteresis characteristic.
Accordingly, there has been a need for an improved logic buffer that reduces the power consumed by the buffer without unacceptably affecting the speed of the buffer and without unacceptably increasing the complexity of the buffer circuit. There has also been a need for a logic buffer that exhibits improved noise immunity.